1. Field of the Invention
The invention relates in general to the field of computing and, more particularly, to buses used in computing. Specifically, the invention relates to a semi-differential bus signaling scheme where the data is referenced to V.sub.ref and the clock is differential.
2. Description of the Related Art
Modern computer systems may contain several microprocessors and microcontrollers connected to each other by a bus. The bus transports data among the microprocessors and other components. The bus is a complex conglomeration of electrical circuits called traces. Traces are wire-like connections that are printed on the top and bottom of a printed circuit board. The number of traces in a bus may give an indication of the size/width of the bus.
FIG. 1 illustrates a computer system with several microprocessors and controllers generally identified as transmitter/receivers (Tx/Rxs) 105-112. Each Tx/Rx 105-112 is connected to traces 113, 114, 116, and 117 in a common bus 115 by four lines (e.g., 118-121). The traces 113 and 114 represent lines in the bus that are solely dedicated to transporting data. Larger amounts of data could be transported by increasing the number of data traces on the bus 115. The trace 116 is a line dedicated to transporting strobe signals, which are clock signals that are transmitted simultaneously or have a predetermined delay with the data signals. The inverse of the strobe signals (strobe*) are transported on the trace 117. Strobe and strobe* signals are used to time-synchronize data appearing as pulses at the receivers 105-112. The strobe signal and strobe* signal are generated by the transmitter and are often implemented to avoid the data received from having to wait for a master common clock (i.e., a main clock signal for the computer system).
When the Tx/Rx 105 transmits data to the Tx/Rx 110, the Tx/Rx 105 takes control of the bus (i.e., become the bus master). The Tx/Rx 105 then places the data on its data lines 120-121. Since these lines are connected to the data traces 113-114 of the bus 115, the data from the Tx/Rx 105 is placed on the bus 115. Similarly, a clock signal is sent to the bus 115 from the Tx/Rx 105 on the line 119 and an inverted clock signal (clock*) is sent on the line 118. The Tx/Rx 110 is also connected to the common bus 115 by the lines 122-125. The clock signal on the line 124 and the clock* signal on the line 125 enable the Tx/Rx 110 to receive the data during a transition of the clock signal.
Typically, signals transmitted within a given computer system experience noise. One source of noise is "ground bounce," which is the shifting of a voltage level designated as ground. "Ground bounce" can cause other signals that are referenced to ground to fluctuate. Other sources of noise include "cross talk" and power supply "dips". Typically, digital components are designed with a specific noise margin. If the voltage levels of the signals go outside the noise margin, the device may not function properly. Thus, it is beneficial to minimize the amount of noise present in order to increase the likelihood of operating a given device within its designated noise margin.
FIG. 2 illustrates a conventional trip point detection system that uses a pseudo-differential bus signaling scheme. A data signal, clock signal, and clock* signal are transmitted from a Tx/Rx 200 to a Tx/Rx 205 by the bus traces 206, 208, and 210, as shown. The Tx/Rx 205 includes three differential amplifiers 207, 209, 211. The differential amplifier 207 compares the voltage level of the data signal on the trace 206 to a reference voltage level. If the voltage level of the data signal is higher than the reference voltage level, the differential amplifier 207 identifies the signal as being in a "high" state. Similarly, if the voltage level of the data signal is less than the reference voltage level, the data signal is designated as being in a "low" state. The clock signal and the clock* signal are similarly compared to the reference voltage by the amplifiers 209 and 211, respectively.
By comparing the signals at the Tx/Rx 205 to a reference voltage, a "good" trip point can be determined. When the noise is within the noise margin, the voltage level of the output signal does not change spuriously. If noise within the noise margin is added to a signal designated as a "low," the voltage level of the additional noise does not cause the total voltage level of the signal to exceed the reference voltage. Thus, the state of the signal, even though it includes noise, remains "low."
Ideally, V.sub.ref remains constant throughout the operation of the device because it is a DC (i.e., direct current) signal. In reality, a small AC (i.e., alternating current) component of V.sub.ref causes it to fluctuate. Since V.sub.ref is the trip point for the differential amplifiers 207, 209, and 211, the shifting of V.sub.ref causes the trip point to shift. For example, if V.sub.ref shifts high as shown at position 305, the trip point of the data would generally be higher, causing the data to be received at a later time. The presence of noise indicated by the shifting of V.sub.ref can become more problematic when the transition time of the inputs to the differential amplifiers 207, 209, 211 is very slow (i.e., the slope of the signal is not steep). The strobe signal and the strobe* signal experience the same kind of fluctuations resulting from fluctuations in V.sub.ref.
FIG. 3 illustrates the timing diagrams at the Tx/Rx 205 for the output signals of the amplifiers 207, 209, and 211 (time is increasing from left to right in each of the diagrams). An output data signal 300 is defined with respect to the reference voltage V.sub.ref. A noise factor labeled .delta..sub.noise is representative of the collection of noise terms that are present. The noise factor .delta..sub.noise includes ground bounce, cross-talk (i.e., the influencing of one signal by another signal), power supply dips, and intersymbol interference (i.e., the presence of previous data influencing present data). Since the noise is assumed to be symmetric, the maximum and minimum levels of the output signal are V.sub.ref+.delta.noise and V.sub.ref-.delta.noise, respectively.
As shown in FIG. 3, a nominal (i.e., ideal) data window is defined from the ideal V.sub.ref position 310 on the data signal to the ideal V.sub.ref position 315 on the strobe signal. The nominal data window 324 is defined as the window of time in which valid data can be received. Fluctuations of V.sub.ref resulting from noise can cause the size of the data window to be reduced significantly even though a pseudo-differential bus signaling scheme is used. For example if V.sub.ref jumps to position 305 on the data signal and position 320 on the strobe signal, the resulting effective data window 322 is considerably smaller than the nominal data window 324. The effective data window 322 has suffered reductions resulting from the noise in both of the strobe signals and the data signal.
Thus, it would be beneficial to have a bus signaling scheme that could reduce the noise present in a signal and is capable of overcoming the shortcomings of conventional methods.